1. Field of the Invention
The present invention relates to a resistance change memory device in which each of memory cells is formed by connecting a storage element, whose resistance changes according to the applied voltage, and an access transistor in series, and which is operated by reversing the polarity of a voltage applied to the storage element between data write and erase operations. The present invention also relates to an operation method of the resistance change memory device.
2. Description of the Related Art
Two types of resistance change memory devices are known, one in which a voltage of the same polarity is applied to the storage elements of the memory cells both during data write and erase operations, and another in which the polarity of an applied voltage is reversed between data write and erase operations. The former will be hereinafter referred to as a unipolar voltage-operated resistance change memory, and the latter a bipolar voltage-operated resistance change memory.
A so-called phase change memory (for example, refer to PCT Patent Publication No. WO2005/098952) is known as a unipolar voltage-operated resistance change memory.
As a bipolar voltage-operated resistance change memory, on the other hand, a resistance change memory device is well known which has, for each memory cell, a storage element whose resistance changes as a result of the injection or withdrawal of conductive ions into or from an insulating film (for example, refer to K. Aratani, etc. “A Novel Resistance Memory with High Scalability and Nanosecond Switching,” Technical Digest IEDM 2007, pp. 783-786).
The storage element has a layered structure in which a layer adapted to supply the conductive ions and an insulating film are formed between two electrodes. The change in resistance of the storage element occurs in a reversible manner as a result of the migration of the conductive ions. This migration is caused by the application of a bipolar voltage.
A storage element (1R) having such a configuration and an access transistor AT (1T) are formed in a memory cell adapted to store one bit of information. A number of 1T1R memory cells are arranged in a matrix form to make up a memory cell array.